Arteris has expanded its multi-die semiconductor design portfolio with the launch of FlexGen Multi-Die, aimed at chiplet-based architectures for AI and high-performance computing.
The addition brings a non-coherent interconnect option to Arteris' existing multi-die lineup, which includes Ncore Multi-Die for cache-coherent systems, as well as Magillem integration automation and Cycuity hardware security tools.
Chipmakers are increasingly shifting from monolithic system-on-chip designs to multi-die layouts as they work around the physical and economic limits of single-die chips. That approach allows different chiplets to be built on different process technologies, but it also creates a new challenge: data that once moved within a single die must now cross chip boundaries.
Arteris' approach extends network-on-chip connectivity across those boundaries so multiple dies can operate as a unified architecture. FlexGen Multi-Die is designed for non-coherent AI and HPC systems, while Ncore Multi-Die targets designs that require cache coherence across multiple dies.
The new product supports bidirectional transactions over a single UCIe PHY and can reduce PHY area, power, and I/O requirements by up to 50%. It also includes virtual channel link technology and quality-of-service mechanisms to manage traffic priority over shared die-to-die links.
K. Charles Janac, President and Chief Executive Officer of Arteris, described the shift as a structural change in chip design.
"Multi-die architectures represent one of the most important changes in semiconductor design since the introduction of the SoC itself," said Janac.
"As systems expand beyond the boundaries of a single piece of silicon, the challenge is no longer simply connecting chiplets; it is preserving the intelligence of the architecture across them. Our goal is to help engineering teams gain the benefits of multi-die architectures without having to reinvent the system every time they divide it across another piece of silicon," Janac added.
Customer demand
The expansion comes as demand for AI computing puts more pressure on chip designers to scale systems beyond the practical size of a single die. Some Arteris customers are already using its technology to move existing architectures from single-die implementations to multi-die products.
AMD pointed to that trend in comments on the launch.
"As agentic AI workloads continue to expand across cloud infrastructure, edge, and endpoint devices, multi-die architectures are becoming increasingly important for balancing performance, scalability, and development efficiency," said Jason Miller, Senior Director of Silicon Design at AMD.
"Solutions that simplify system integration while preserving bandwidth and performance across chiplets help engineering teams accelerate innovation and bring differentiated products to market faster. Arteris' continued expansion of its multi-die portfolio supports the flexibility and productivity required for our next-generation data center, client, gaming, and embedded compute products," Miller added.
Socionext also signaled support, though its remarks highlighted the sector's strategic direction as much as Arteris' product set.
"The future of advanced semiconductor design is inherently multi-die," said Daisuke Murakami, Executive Chief Engineer, Global Leading Group, at Socionext.
"By collaborating with Arteris on its UCIe-based multi-die solution, we gain early access to technologies that simplify chiplet integration while enabling the scalability, bandwidth, and efficiency needed for next-generation AI, automotive, and data-center SoCs," Murakami said.
Ecosystem push
Beyond individual products, Arteris is positioning itself within a broader chiplet ecosystem built around interoperability among interconnects, chiplet IP, packaging technologies, and design tools. That is becoming more important as semiconductor companies seek to combine dies from different suppliers and process nodes in a single package.
Several industry partners used the announcement to underline the need for compatible standards and validated interfaces. Synopsys said interoperability had been validated between its UCIe IP and Arteris Ncore cache-coherent NoC IP for multi-die designs. UniVista also said it was working with Arteris to validate interoperability between its UCIe IP and Arteris Ncore Multi-Die.
Cadence linked the collaboration to a broader push in AI system design.
"Physical AI systems require right-sized inference and scalable architectures that seamlessly integrate diverse compute technologies while meeting stringent power, performance, safety, security, and reliability requirements," said David Glasco, Vice President of R&D, Silicon Solutions Group, at Cadence.
"By combining the comprehensive Cadence Physical AI platform, IP, and security solutions with Arteris' NoC IP, our collaboration enables accelerated silicon realization and trusted system deployment from cloud to edge. This reusable foundation helps customers scale physical AI systems more efficiently, reduce development risk, and speed time to market. Together, Cadence and Arteris provide a seamless path from specification to silicon to deployment, accelerating innovation across the physical AI ecosystem," Glasco said.
Silitronics described the work in terms of open chiplet architectures and manufacturable systems.
"An open chiplet ecosystem requires architectural frameworks that simplify the integration of specialized dies into scalable, manufacturable systems," said Suresh Subramaniam, PhD, Chief Technology Officer of Systems and Advanced Packaging at Silitronics.
"We plan to leverage Arteris FlexGen technology in our development of an OCP-derived chiplet architecture, combining intelligent die-to-die connectivity with Silitronics' system-level design, advanced packaging, and heterogeneous integration capabilities to help customers bring differentiated multi-die solutions to market faster," Subramaniam said.
FlexGen Multi-Die is available to early-access partners and strategic customers, adding a new option for semiconductor groups looking to extend established architectures across multiple dies without redesigning how traffic moves through the system.