Renesas develops 28nm MCU with virtualisation-assisted functions
Renesas Electronics announced the development and successful operation verification of an automotive test chip as a technological stepping stone toward the realisation of next-generation automotive-control flash Microcontrollers (MCUs) employing a 28 nanometer (nm) low-power process.
The MCU features four 600 megahertz (MHz) CPUs with a lock-step mechanism and a large 16 MB flash memory capacity.
New electrical/electronic (E/E) architectures are driving demand for the integration of multiple electronic control units (ECUs) into single ECUs that support multiple functions.
Achieving this level of integration requires higher performance, reduced power consumption, and large capacity flash memory.
Automotive MCUs are also challenged with the requirements of running software components with varying safety integrity levels simultaneously and without mutual interference. In addition to requiring software independence, automotive control demands real-time responsiveness.
To meet these next-generation requirements, Renesas has developed new technologies led by virtualisation-assisted functions for automotive-control MCUs, as demonstrated in the new test chip.
Hardware-based virtualisation-assisted functions
Typically, software-based (hypervisor) virtualisation requires greater processing time due to the need to emulate hardware virtually.
The increased processing time required by the hypervisor to change between CPU states (context switching), deliver interrupts, poses problems for automotive-control MCUs that must maintain real-time responsiveness.
To address this issue, Renesas developed a hardware-based virtualisation-assisted function that dramatically reduces the virtualization overhead, thereby boosting responsiveness.
It allows software components with varying safety integrity levels to operate independently, making it possible for the MCU to deliver both virtualisation and real-time performance as required by ASIL D.
Standby-resume built-in self-test (BIST) function
BIST functions are a requirement in achieving ASIL D safety integrity levels, to enable the MCU to perform self-diagnostics on the MCU while it is running.
One way to avoid disturbing a CPU processing period would be to perform self-diagnostics in the period between when the MCU enters the standby state and when the resume occurs. However, there is a limitation regarding current fluctuations, so the increase in the current fluctuation rate caused by resume due to self-diagnostics is a concern.
Renesas has developed standby-resume BIST (SR-BIST) to minimise the current fluctuation rate. SR-BIST runs before the CPU begins operating each time there is a transition from standby to resume.
To ensure rapid startup, the on-chip oscillator supplies a clock for the fault diagnostics. An N/M divider is used to gradually increase the frequency of the clock, reducing the current fluctuation rate (Note 2) when SR-BIST is executing. As a result, it allows functional safety that meets the requirements of ASIL D.
SGMII-compliant Gigabit Ethernet interface with 5V support
The next-generation of autonomous driving cars and connected cars will employ large numbers of sensors and cameras, which will require Ethernet as a high-speed communication interface to handle the enormous amount of data generated by these devices.
Nevertheless, automotive MCU interface circuits continue to rely on 5V transistors for reliability reasons tied to voltage surges.
Therefore, Renesas has developed a Gigabit Ethernet interface using 5V transistors that supports the Serial Gigabit Media Independent Interface (SGMII) standard and provides excellent electrical noise tolerance.
To deal with the deterioration of the signal bandwidth due to the use of 5V transistors, dedicated circuits were added for receiver and driver. This results in signal quality that complies with the SGMII standard
