XConn & ScaleFlux boost CXL 3.1 memory for AI & cloud

XConn Technologies and ScaleFlux have announced the successful interoperability and performance optimisation between the XConn CXL 3.1 switch and the ScaleFlux MC500 CXL 3.1 Type 3 memory controller.

This technical collaboration is intended to support memory disaggregation and pooling capabilities in artificial intelligence (AI) and cloud infrastructure, using Compute Express Link (CXL) 3.1. The combined solution is positioned to improve composable memory performance, leveraging XConn's hybrid PCIe / CXL switch and the error correction and reliability features built into the ScaleFlux MC500 controller.

The XConn CXL 3.1 switch and ScaleFlux MC500 controller have been demonstrated together as part of a fully functional, disaggregated memory platform. This demonstration aims to provide the industry with an example of solutions capable of supporting growing demands for scalability, low latency, and reliability within AI and cloud deployments.

Gerry Fan, Chief Executive Officer of XConn Technologies, said,

"This is a major step forward for the Compute Express Link (CXL) ecosystem. By optimising our CXL 3.1 switch to work seamlessly with ScaleFlux's MC500 memory controller, we're giving customers a production-ready path to unlock the full potential of CXL-based memory pooling and disaggregation in AI and cloud environments."

The ScaleFlux MC500 CXL 3.1 Type 3 controller has been developed in conjunction with hyperscale data centre operators, memory manufacturers, and processor vendors. The controller features a list decoding Error Correcting Code (ECC) architecture aimed at providing reliability, availability, and serviceability (RAS) for DRAM-based memory systems. It also includes production grade firmware, intended for rapid deployment among data centres adopting CXL memory infrastructure.

Hao Zhong, Chief Executive Officer and Co-founder of ScaleFlux, commented,

"Our partnership with XConn underscores our commitment to building a robust and interoperable CXL ecosystem. The combination of our MC500 controller's advanced ECC technology and XConn's hybrid CXL 3.1 switch offers data centres and AI infrastructure providers a highly reliable, low-latency solution to efficiently scale memory capacity and bandwidth for their AI and enterprise applications."

The announcement also saw AMD, a leading supplier of processors to the data centre market, signal its support for ongoing efforts around the CXL ecosystem. In reference to the joint project, Raghu Nambiar, Corporate Vice President, Data Centre Ecosystems and Solutions at AMD, stated,

"CXL is critical to accelerating the development of next-generation memory and compute technologies powering critical AI and HPC workloads. Our collaboration with XConn and ScaleFlux strengthens ecosystem interoperability efforts that enable memory disaggregation and infrastructure flexibility for the modern AI data centre."

XConn noted that it continues to pursue the adoption of CXL 3.1 infrastructure, focusing on standards-based development, collaboration within the technology ecosystem, and solutions suited to the requirements of AI and cloud applications at scale.

XConn representatives have also outlined plans to participate in broader discussions regarding CXL's impact on server memory infrastructure. Jianping Jiang, Senior Vice President, Business Development, is scheduled to speak on a panel session titled "How CXL Transforms Server Memory Infrastructure."

Additionally, XConn announced it will deliver an end-to-end PCIe Gen 6 demonstration during the same period, further illustrating its ongoing product roadmap for high-performance data centre interconnects.